Conventionally, as a part of compression coding technique for still images and moving images, a method using an entropy coding technique by variable-length code is well known. This technique is also adopted in the JPEG (Joint Photographic Expert Group) coding and the MPEG (Moving Picture Expert Group) coding as international standards.
FIG. 12 is a block diagram showing an example of a variable-length decoding apparatus for the generally-used JPEG coding method as a still image coding method.
In FIG. 12, in coded data inputted in a shifter 1201, a variable-length code or additional bits are found-for access by each cycle. The coded data where the variable-length code/additional bits are found by each cycle is inputted into a comparator array 1203. In a current cycle, the coded data is compared with minimum code words of code lengths corresponding to variable-length code table of coded data inputted from a minimum code word & initial data memory 1202. The comparator array 1203 has comparators corresponding to the number of code lengths existing in the variable-length code table, and the bit lengths of the respective comparators respectively correspond to the existing code lengths. For example, if the variable-length code table has 16 types of code words of 1 to 16 bit code lengths, the number of comparators is 16. The respective comparators perform data-size comparison between the respective minimum code words with the input coded data in parallel. Each comparator outputs true (1) if the input coded data is greater than the minimum code word. The outputs from the comparator array 1203 are inputted into a priority encoder 1204 which assigns the highest priority to the output from the 1-bit comparator, and a highest priority comparator is obtained from the comparators which outputted comparison result as false (0).
In the JPEG coding, the number of bits of the comparator determined by the priority encoder 1204 becomes the code length, and is outputted via an MUX 1205 as a shift amount in the shifter 1201. Further, symbol data RRRR/SSSS (run/category) are stored, in the order of their occurrence, in a symbol memory 1207. Initial data corresponding to the code length as the output from the priority encoder 1204 is outputted from an MUX 1206, and added to the coded data as a frequency of occurrence. This becomes an address to the symbol memory 1207.
Note that the initial data is obtained by the following expression by each code length.                               ADDR          =                                    VLC              ⁢                                                          ⁢              in                        -                          VLC              ⁢                                                          ⁢              min                        +            ADDRbase                                                        =                                    VLC              ⁢                                                          ⁢              in                        +                          (                              ADDRbase                -                                  VLC                  ⁢                                                                          ⁢                  min                                            )                                             
In the above expression, ADDR is an address in the symbol memory 1207; VLCin, coded data in which the variable-length code is currently found by the shifter 1201; VLCmin, a minimum code word in the same code length; and ADDRbase, an address of the minimum code length word in the symbol memory 1207. The right term (ADDRbase−VLCmin) corresponds to the initial data.
In the next cycle, the decoding symbol data RRRR and SSSS are outputted from the symbol memory 1207. The value of SSSS also becomes a shift amount of a right shifter 1208. Thus, the output data from the shifter 1201 where the additional bits are found is right-bit shift processed by the right shifter 1208, as output additional bits. As the value of SSSS equals the additional bit length, it is inputted as a shift amount into the shifter 1201, to shift out the additional bits.
FIG. 13 is a block diagram showing an example of a variable-length decoding apparatus for the MPEG1 or MEPG2 coding method generally-used as a moving image coding method. The variable-length decoding apparatus performs decoding processing on an Intra picture (I-Picture). In an Intra picture, image data is encoded by three types of variable-length coding methods, i.e., variable-length codings for DC and AC coefficients and fixed-length coding for AC coefficients.
The DC coefficient coding is very similar to the DC coefficient coding in the JPEG coding. A variable-length code which was found in a shifter 1301 is inputted into the DC decoder 1309. The DC decoder 1309 has a comparator array and a priority encoder as in the case of FIG. 12. At the same time, minimum code words of respective code lengths of a variable-length code table for Differential DC size are inputted into the comparator array from the minimum code word array 1308, and the input data are compared. The priority encoder obtains a code length from the comparison results, and an address to a table RAM 1310 holding the Differential DC sizes is generated. Thus, the obtained code length becomes a shift amount to a right shifter 1311. Then variable-length code of the next additional bits is obtained.
In the next cycle, the Differential DC size outputted from the table RAM 1310 is inputted as decoded data into a-selector 1312. Further, in the right shifter 1311, right-bit shift is performed with the Differential DC size value as a shift amount, and the data is inputted as additional bits into a selector 1312. In the figure, DC—SIZE indicates the Differential DC size; and DC—DIFF denotes additional bits.
On the other hand, in the case of AC coefficient coding, by RUN/LEVEL combination, input data is decoded by different decoding methods depending on whether the data is variable-length coded data or fixed-length coded data. If it is detected in the output from the shifter 1301 that the data is fixed-length coded data, an escape decoder 1306 decodes the data into RUN/LEVEL data. The escape decoder 1306 does not require a symbol memory, therefore it can be realized with a small-scale circuit construction.
On the other hand, in the case of variable-length coding, decoding processing is performed by using an AC coefficient symbol memory 1307. The coded data inputted from the shifter 1301 is compared with a variable-length code word stored in a variable-length code word and code length memory 1302 by a comparator 1303. The comparison processing is continued until coincidence of number of clocks is detected by each frequency of occurrence. If coincidence is detected in the comparator 1303, the number of clocks from the start of comparison to the current time is outputted from a decoder 1305 to an address counter 1304. This count value becomes the frequency of occurrence, and becomes an address to the AC symbol memory 1307. Further, in the cycle, the code length outputted from the variable-length code word and code length memory 1302 is outputted as a shift amount of the shifter 1301. In the next cycle, RUN/LEVEL data is outputted from the AC coefficient symbol memory 1307 and inputted into a selector 1312. The selector 1312 selects an input signal in accordance with the variable-length coding method and outputs decoded data by the variable-length coding apparatus.
In recent years, there is an increasing need for a system capable of handling both still and moving images. In this case, a generally-used still-image decoding technique is the JPEG coding method as shown in FIG. 12, and a generally-used moving-image decoding technique is the MPEG coding as shown in FIG. 13. It is possible to construct a decoding apparatus by using these constructions in FIGS. 12 and 13 in parallel, however, in such case, the apparatus requires a huge/enormous circuit scale. In addition, as a RAM, at least the symbol memory 1207 in FIG. 12, the DC coefficient DC—SIZE table 1310 and the AC coefficient symbol memory 1307 in FIG. 13 are respectively required. The necessary memory capacity increases, which increases the apparatus size, costs and the like.